Assessing Triple Modular Redundancy for Wide-Link, Low-Latency NoC Routers: Reliability and Physical Design Challenges
2026-08-21 • Hardware Architecture
Hardware Architecture
AI summaryⓘ
The authors studied ways to protect the communication network inside AI chips from errors caused by harsh environments, like cosmic rays. They tested three different methods of adding extra copies (Triple Modular Redundancy or TMR) to catch and fix errors in a very fast, wide-data router design. Their experiments showed that only the full TMR method completely stopped errors, though it initially required much more chip area. However, when the full TMR router was placed inside a whole AI chip, the extra space and power needed became much smaller, showing this approach is practical for real devices.
Network-on-Chip (NoC)Physical AI acceleratorsSingle-Event Effects (SEE)Single-Event Upset (SEU)Single-Event Transient (SET)Triple Modular Redundancy (TMR)RTL-to-GDSIITSMC 7nm technologyFault injectionGEMM benchmark
Authors
Chen Wu, Michael Rogenmoser, Luca Benini, Angelo Garofalo
Abstract
Protecting the Network-on-Chip (NoC) of physical-AI tile-based accelerators deployed in harsh environments against single-event effects (SEEs) is paramount for preventing NoC failures that can lead to deadlocks and silent data corruption (SDC). Prior work on reliable NoCs has largely focused on narrow links (e.g., 32-bit), deeply pipelined routers, and single-event upsets (SEUs). However, the state of the art has evolved toward low-latency NoC routers with ultra-wide links, implemented on advanced technology nodes and operating at frequencies above 1 GHz. We evaluate the cost and reliability trade-offs of implementing Triple Modular Redundancy (TMR) at three granularities (coarse, state-only, and full) for a 2-cycle-latency NoC router with 512-bit wide links. We carry out RTL-to-GDSII physical design in TSMC 7nm technology, as well as both RTL- and netlist-level SEU and SET fault injection campaigns. We evaluate the three TMR approaches in terms of reliability, cost, and physical design strategies, further extending the assessment from a standalone router to a full AI acceleration tile. Our results show that state-only and coarse-grained TMR do not provide sufficient protection against SEEs, whereas full TMR eliminates all observed failures across more than one million injected faults per experiment. Although the standalone full-TMR router incurs a 7.04x area overhead, this cost is drastically amortized once integrated into a complete AI accelerator tile with processors and local L1 memories: the same design adds only 16.8% area and 15.2% power consumption under a GEMM benchmark at the system level, with the critical path of the tile entirely unaffected. These results demonstrate that advanced technology nodes provide sufficient routing capacity to make full TMR a practical and deployable solution for protecting NoCs in Physical AI systems operating in harsh environments.