ArchAgent v2: A Case Study with the Data Prefetching Championship
2026-08-10 • Artificial Intelligence
Artificial IntelligenceHardware Architecture
AI summaryⓘ
The authors developed ArchAgent v2, a system that helps design smarter ways for computers to fetch data faster by automatically exploring many possible designs. They improved their earlier version by breaking down the problem into smaller parts and using feedback on hardware size during the search. Tested in a competition, their system found a three-level prefetching method that outperforms human-designed solutions. However, they note that designing for multi-core systems is still hard because simulations take a long time. Their work gives insights into how automated tools can help computer architects create better hardware designs.
agentic artificial intelligencemicroarchitecturedata prefetchingevolutionary searchcache replacement policieshardware realizabilityinstruction per cycle (IPC)simulation latencymulti-core processorsarchitecture design automation
Authors
Abraham Gonzalez, Raghav Gupta, Akanksha Jain, Hanna Alam, Alexander Novikov, Po-Sen Huang, Matej Balog, Marvin Eisenberger, Sergey Shirobokov, Ngân Vũ, Hank Levy, Borivoje Nikolić, Sagar Karandikar, Martin Dixon, Parthasarathy Ranganathan
Abstract
Agentic artificial intelligence has shown great promise in automating algorithm design, but scaling similar techniques to computer microarchitecture discovery remains challenging due to vast search spaces, strict hardware budgets, and long simulation times. In this work, we present ArchAgent v2, a framework which scales automated microarchitecture search to multi-level data prefetching. While the original ArchAgent successfully discovered single-level cache replacement policies in competition settings, it does not scale to multi-level prefetching where the design space and degrees of freedom are larger. To overcome this, we introduce two new additions to ArchAgent: a cascaded evolutionary search that subdivides the design space by sequentially evolving and freezing prefetchers at individual cache levels, and a hardware-realizability feedback loop that embeds real-time size-estimation directly into the evolution process. Evaluated under identical rules of the 4th Data Prefetching Championship (DPC4), ArchAgent v2 automatically designs a three-level prefetcher that outperforms the winning hand-designed solution, further demonstrating automated agentic discovery as a useful tool for computer architects. Our discovered policy achieves a 3.8\% geometric mean IPC speedup over the baseline overall and a 0.3\% improvement over the prior champion, BertiGO. On low-bandwidth single-core configurations, our policy yields a 4.6\% performance speedup compared to only 2.6\% for BertiGO. However, multi-core evolution still remains a significant challenge due to simulation latency impeding evolution speed. Finally, our profiling of an ArchAgent evolution of over 12,000 candidate designs provides key insights into how automated evolutionary agents explore and synthesize complex microarchitectural logic.