Symbolic Polyhedral-Based Energy Analysis for Nested Loop Programs
2026-04-08 • Hardware Architecture
Hardware Architecture
AI summaryⓘ
The authors developed a new way to estimate how much energy programs with nested loops will use when run on special parallel processors. Instead of running slow simulations, they use a symbolic method that predicts energy use based on how the loops are organized and scheduled. Their method works well for different problem sizes and is faster and more scalable than simulations. This helps designers test different setups efficiently and compare different processor arrangements.
symbolic energy analysisnested loopsparallel processor arraysenergy consumption estimationmappingschedulingdesign space explorationiteration spaceaccelerator architectures
Authors
Avinash Mahesh Nirmala, Dominik Walter, Frank Hannig, Jürgen Teich
Abstract
This work presents a symbolic approach for estimating the energy consumption for nested loop programs when mapped and scheduled on parallel processor array accelerator architectures. Instead of simulation-based evaluation, we derive a methodology for symbolic energy analysis that captures the impact of mapping and scheduling decisions of loop nests on processor arrays. We compare our approach against simulation-based results for selected benchmarks and varying sizes of the iteration spaces. Whereas the latter are not scalable, our symbolic analysis is shown to be independent of the problem size. The presented evaluation methodology can be beneficially used during the design space exploration of mapping and scheduling decisions, for studying the influence of array size variations, and for comparisons with other loop nest accelerator architectures.