See it to Place it: Evolving Macro Placements with Vision-Language Models
2026-03-30 • Machine Learning
Machine Learning
AI summaryⓘ
The authors propose using Vision-Language Models (VLMs), which are good at understanding images and language, to help place large components on computer chips more efficiently. They created VeoPlace, a system that uses a VLM to suggest where to put pieces on the chip, then improves those suggestions through a process like evolution. Without needing extra training, VeoPlace outperformed previous learning methods on most tests and also helped improve another chip placement tool called DREAMPlace. This work shows a new way to use advanced AI models for designing computer chips.
Vision-Language ModelsMacro PlacementChip FloorplanningSpatial ReasoningEvolutionary SearchWirelengthLearning-based PlacementDREAMPlaceElectronic Design AutomationOptimization
Authors
Ikechukwu Uchendu, Swati Goel, Karly Hou, Ebrahim Songhori, Kuang-Huei Lee, Joe Wenjie Jiang, Vijay Janapa Reddi, Vincent Zhuang
Abstract
We propose using Vision-Language Models (VLMs) for macro placement in chip floorplanning, a complex optimization task that has recently shown promising advancements through machine learning methods. Because human designers rely heavily on spatial reasoning to arrange components on the chip canvas, we hypothesize that VLMs with strong visual reasoning abilities can effectively complement existing learning-based approaches. We introduce VeoPlace (Visual Evolutionary Optimization Placement), a novel framework that uses a VLM, without any fine-tuning, to guide the actions of a base placer by constraining them to subregions of the chip canvas. The VLM proposals are iteratively optimized through an evolutionary search strategy with respect to resulting placement quality. On open-source benchmarks, VeoPlace outperforms the best prior learning-based approach on 9 of 10 benchmarks with peak wirelength reductions exceeding 32%. We further demonstrate that VeoPlace generalizes to analytical placers, improving DREAMPlace performance on all 8 evaluated benchmarks with gains up to 4.3%. Our approach opens new possibilities for electronic design automation tools that leverage foundation models to solve complex physical design problems.