NL2GDS: LLM-aided interface for Open Source Chip Design
2026-03-05 • Hardware Architecture
Hardware ArchitectureComputers and SocietyLogic in Computer Science
AI summaryⓘ
The authors created a system called NL2GDS that turns simple natural language descriptions of hardware into actual hardware designs and layouts. Their method uses advanced language models to write hardware code and then automatically generate the physical chip design. Testing on standard benchmarks showed their designs use less area, have shorter delays, and consume less power than usual methods. This approach could make chip design easier and faster for more people.
hardware designnatural language processinglarge language modelsregister-transfer level (RTL)GDSII layoutASIC designOpenLane flowHDL generationsynthesisISCAS benchmarks
Authors
Max Eland, Jeyan Thiyagalingam, Dinesh Pamunuwa, Roshan Weerasekera
Abstract
The growing complexity of hardware design and the widening gap between high-level specifications and register-transfer level (RTL) implementation hinder rapid prototyping and system design. We introduce NL2GDS (Natural Language to Layout), a novel framework that leverages large language models (LLMs) to translate natural language hardware descriptions into synthesizable RTL and complete GDSII layouts via the open-source OpenLane ASIC flow. NL2GDS employs a modular pipeline that captures informal design intent, generates HDL using multiple LLM engines and verifies them, and orchestrates automated synthesis and layout. Evaluations on ISCAS'85 and ISCAS'89 benchmark designs demonstrate up to 36% area reduction, 35% delay reduction, and 70% power savings compared to baseline designs, highlighting its potential to democratize ASIC design and accelerate hardware innovation.